The present invention disclosed herein relates to a voltage controlled oscillator and phase locked loop comprising the same.
Recently, in designing IC (Integrated Circuit) decreasing power consumption and increasing energy efficiency has become an important issue. To solve this problem, lowering power voltage method has been used and therefore designing to drive PLL (Phase-Locked Loop) in a low power voltage is in center of attention.
The PLL is a required circuit in the wire and wireless communication. It is used to get the same frequency with the reference signal by sub-circuit or to get a stable obtained frequency. The PLL function differs depending on a power noise and especially the VCO (Voltage Controlled Oscillator) is sensitive to the power noise that its oscillation frequency differs depending on the power noise.
Generally, a power voltage regulator is used to compensate a power noise. However, this requires an additional transistor stacking in the circuit and thereby is not appropriate at the low power voltage since it causes a problem in a power head room.